transcript on
if {[file exists rtl_work]} {
	vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work

vlog -vlog01compat -work work +incdir+D:/WorkStation/DDS/Entry_Ver/Software/FPGA {D:/WorkStation/DDS/Entry_Ver/Software/FPGA/DDS_V1.v}
vlog -vlog01compat -work work +incdir+D:/WorkStation/DDS/Entry_Ver/Software/FPGA {D:/WorkStation/DDS/Entry_Ver/Software/FPGA/DDS_CTL.v}
vlog -vlog01compat -work work +incdir+D:/WorkStation/DDS/Entry_Ver/Software/FPGA {D:/WorkStation/DDS/Entry_Ver/Software/FPGA/FSMC.v}
vlog -vlog01compat -work work +incdir+D:/WorkStation/DDS/Entry_Ver/Software/FPGA {D:/WorkStation/DDS/Entry_Ver/Software/FPGA/DDS_RAM.v}
vlog -vlog01compat -work work +incdir+D:/WorkStation/DDS/Entry_Ver/Software/FPGA {D:/WorkStation/DDS/Entry_Ver/Software/FPGA/PLL.v}
vlog -vlog01compat -work work +incdir+D:/WorkStation/DDS/Entry_Ver/Software/FPGA/db {D:/WorkStation/DDS/Entry_Ver/Software/FPGA/db/pll_altpll.v}

vlog -vlog01compat -work work +incdir+D:/WorkStation/DDS/Entry_Ver/Software/FPGA/simulation/modelsim {D:/WorkStation/DDS/Entry_Ver/Software/FPGA/simulation/modelsim/DDS_V1.vt}

vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc"  DDS_V1_vlg_tst

add wave *
view structure
view signals
run 5 us
